Leadframes are one well known way of providing electrical interconnects for an integrated circuit (“IC”) device in the creation of a chip scale package (“CSP”). In general, leadframes and other forms of electrical interconnects can comprise metallic traces or “leads” that permit electrical communications to and from various electrical contact points on an associated die or other IC device. Although there are a variety of different types of electrical interconnects, and leadframes in particular, a leadless leadframe package (“LLP”) is one example of a relatively recent IC package design that contemplates the use of a metal substrate in the formation of a CSP.
As shown in FIGS. 1A through 1C, a typical set of LLPs can involve the formation of a copper leadless leadframe strip or panel 10 that is patterned to define a plurality of device arrays or matrices 11 of individual semiconductor device areas or electrical interconnect patterns 12. Each device area 12 comprises an electrical interconnect pattern that includes a plurality of contact regions 13 arranged around the circumference of an attach pad 14. Fine tie bars 15 may also be used to support the contact regions 13 and attach pads 14, although such tie bars may be unnecessary in some LLP or other general leadframe designs. As shown, there are five separate device arrays 11 in panel 10, twelve individual device areas 12 in each device array 11, and ten contact regions 13 in each individual device area. However, it will be readily appreciated that any given panel may have more or fewer device arrays, that any given device array may have more or fewer individual electrical interconnect patterns, and that any given device area may have more or fewer contacts or contact regions, as may be desired for a particular design.
Panel 10 is typically formed by etching a relatively thin conductive metal layer, such as copper, into specific electrical interconnect patterns, as shown. Such a metal layer for panel 10 tends to have a thickness of about 100 to 300 microns, such that the entire finished panel is relatively thin, yet still has enough structural integrity to be transported about and processed without collapsing or breaking. Although the primary function of the various patterns, that being to provide electrical interconnects between components, can be accomplished with patterns that are substantially thinner than those in panel 10, the typical thicknesses of these panels are typically much larger, such that the panels are sturdy enough to be readily processed. One drawback of panels that are thicker than necessary for their primary function, however, is that additional material is used, which can drive up materials costs. The drawback of such added materials costs can be aggravated when such panels are made from more valuable or expensive metals, such as copper, silver and/or gold.
While many IC device leadframes and other electrical interconnect systems have worked well in the past, there is always a desire to provide improved and more cost effective processes for packaging IC devices.